The invention relates to semiconductor memory devices. More particularly, the invention relates to nonvolatile memory devices having extension of a trimming operation by reducing a chip area thereof.
Electrically re-writable nonvolatile memory devices, such as flash memory, are increasingly used in contemporary electronics due to their high integration density and superior performance characteristics. As is conventionally understood, proper operation of a semiconductor memory device requires the definition and maintenance of certain operating voltages.
The level of operating voltages may be precisely defined in a process commonly referred to as “trimming.” The trimming of an operating voltage within a flash memory device may be performed in relation to so-called “trimming data.” Trimming data may be stored, for example, in a predetermined portion of the memory array of a constituent flash memory device. Trimming data may be used to adjust operating voltages within defined modes of operation for the flash memory device (e.g., a read mode, a program mode, a delete mode, etc.). By carefully adjusting operating voltages within a flash memory device, the performance of certain circuitry (e.g., control sense amplifiers, a reference cell, etc.) may be optimized. Trimming improves the consistency with which a flash memory device operates, and may be used to compensate for non-uniformities in the device manufacturing processes.
FIG. (FIG.) 1 is a schematic diagram illustrating a conventional nonvolatile memory device 100. Referring to FIG. 1, nonvolatile memory device 100 includes a trimming cell array 110 storing trimming data, a trimming cell sense amplifier and a write driver 120 sensing the trimming data, and a trimming cell latch 130 storing the sensed trimming data. These circuits generally operate under the control of a trimming cell control logic unit 140.
Sensed trimming data stored in trimming cell latch 130 is provided to various trimming circuits including a read trimming circuit 150, a program trimming circuit 160, a deletion trimming circuit 170. It may also be provided to an estimation trimming circuit (not shown). Each trimming circuit variously trims certain operating voltages in order to optimize sense amplifiers, reference cells, etc., of nonvolatile memory device 100.
Trimming circuits 150, 160 and 170 respectively include trimming units 151, 161 and 171 performing defined trimming operations in accordance with trimming control signals (e.g., signal_1, signal_2 . . . , signal_N) derived from the trimming data provided from trimming cell latch 130. Trimming circuits 150, 160 and 170 may be required to temporarily vary (or adjust) the trimming control signals in relation to the trimming data provided from trimming cell latch 130. For example, trimming circuits 150, 160 and 170 may be required to vary respective trimming control signals according to certain “down-trimming” or “up-trimming” control data. Such trimming control data may be externally provided in response to any number of control factors.
Variance of trimming control signals may be achieved within trimming circuits 150, 160 and 170 by means of temporary trimming control logic units 152, 162 and 172 and corresponding summers 153, 163 and 173. Temporary trimming control logic units 152, 162 and 172 respectively receive externally provided control data (e.g., temporary trimming data Ex_Trim_1, Ex_Trim_2 . . . , and Ex_Trim_N), and control operation of summers 153, 163 and 173 to vary the trimming control signals Signal_1, Signal_2 . . . and Signal_N.
However, the incorporation of respective temporary trimming control logic units 152, 162 and 172 and summers 153, 163 and 173 within constituent trimming circuits 150, 160 and 170 increases the overall chip area required to implement nonvolatile memory device 100. Unfortunately, when the number of trimming circuits is limited in conventional nonvolatile memory devices due to concerns over chip area utilization, the number of trimming operations operatively provided within the device must also be reduced.